14.3 生成设计层次报表

  设计层次报表用于露示以后的.ddb设计数据库文件的分级构造。

  实行菜单命令【Reports】/【Design Hierarchy】,生成的设计层次报表情节如次所示:

  Design Hierarchy Report for D:\protel99sebook\sch\scb.ddb

  Documents

  PCB1.DRC

  PCB1.PCB

  PCB2.PCB

  Place1.Plc

  Place2.Plc

  Place3.Plc

  scb.DRC

  scb.lib

  scb.NET

  scb.pcb

  scb.REP

  scb.Sch

  scb.DMP

  14.4 生成网绕样儿子报表

  网绕样儿子报表用于露示电路板中的每壹条网绕走线的长度。实行菜单命令【Reports】/【Netlist Status】,体系己触动翻开文本编纂器,产生相应的网绕样儿子报表,扩展名也为.REP。报表文件情节如次:

  Nets report For Documents\scb.pcb

  On 17-Jun-2003 at 00:26:32

  GND Signal Layers Only Length:1296 mils

  N01 Signal Layers Only Length:221 mils

  N02 Signal Layers Only Length:221 mils

  N03 Signal Layers Only Length:481 mils

  N04 Signal Layers Only Length:180 mils

  N05 Signal Layers Only Length:521 mils

  N06 Signal Layers Only Length:646 mils

  N07 Signal Layers Only Length:646 mils

  N08 Signal Layers Only Length:680 mils

  NetC9_2 Signal Layers Only Length:1684 mils

  NetSW1_16 Signal Layers Only Length:2985 mils

  NetU12_10 Signal Layers Only Length:673 mils

  NetU9_12 Signal Layers Only Length:1269 mils

  NetU9_13 Signal Layers Only Length:1405 mils

  NetXTAL_2 Signal Layers Only Length:1326 mils

  VCC Signal Layers Only Length:1280 mils

  剩意,当对电路板重行布匹线后,又生成的网绕走线长度将会突发变募化。

  14.5 生成记号完整顿性报表

  记号完整顿性报表是根据以后电路板文件的情节和Signal Integrity设计规则的设置情节生成的记号剖析报表。该报表用于为设计者供壹些拥关于元件的电气特点材料。生成报表的操干步儿子如次:

  步儿子1:实行菜单命令【Reports】/【Signal Integrity】。

  步儿子2:实行该命令后,体系将切换到文本编纂器,并在就中产生记号完整顿性报表文件,扩展名为.SIG。如对Scb.PCB文件生成的记号完整顿性报表文件名为Scb.SIG,情节如次:

  Documents\scb.SIG - Signal Integrity Report

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  Designator to Component Type Specification

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